The present invention relates to a processing link control device. More particularly, the invention relates to a processing link control device in a data processing system processing data by executing a main routine and a sub-routine.
Heretofore, as a method in a micro-program computer, micro-instruction, hereinafter referred to as BAL, for Branch and Link, has been widely introduced for branching from the main routine to a sub-routine. The instruction is used to save the return address, which is used for returning to the main routine when branching from the main routine to the sub-routine. Thus, the main routine may be started again by returning the address being saved with another instruction at the output of the sub-routine to the address register when returning from the sub-routine to the main routine. Conventionally, however, the return address specified by the instruction has been determined on a one to one basis. Therefore, there is a limitation on the allocation of the address location of the micro-instruction within the control memory. As a result, it becomes difficult to effectively use the control memory. This results in uneconomical use of the memory.
The principal object of the invention is to provide a processing link control system for data processing equipment which provides efficient and economical use of the memory thereof.
An object of the invention is to provide a processing link control system for data processing equipment, which processing link control system is of simple structure and inexpensive in manufacture.
Another object of the invention is to provide a processing line control system for data processing equipment, which processing link control system functions efficiently, effectively and reliably to select one of a plurality of return addresses by instruction.